The present invention relates generally to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device which can prevent contact loss and a method for manufacturing the same.
Memory devices can be generally grouped into volatile random access memory (RAM), which loses inputted information when power is interrupted; and a non-volatile read-only memory (ROM), which can continuously maintain the stored state of inputted information even when power is interrupted. Examples of volatile RAM include dynamic RAM (DRAM) and static RAM (SRAM); and examples of non-volatile ROM include flash memory devices such as electrically erasable and programmable ROM (EEPROM).
DRAM is well known as an excellent memory device. However, DRAM must have high charge storing capacity. To achieve high storage capacity the surface area of an electrode is often times increased, but the increased surface area makes it difficult to accomplish a high level of integration. Further, in a flash memory device two gates are typically stacked upon each other and require a high operation voltage relative to the power source voltage. Therefore, a separate booster circuit is necessary to supply the voltage required for write and delete operations, which in turn makes difficult to accomplish a high level of integration.
With these constraints in mind, it is highly desirable to develop a memory device having a simple configuration and capable of accomplishing a high level of integration while retaining the characteristics of a typical non-volatile memory device. Recently, phase change memory devices have been recognized as memory devices with the potential to achieve these characteristics.
In a phase change memory device in order to store information a phase change is imposed on a phase change layer interposed between a bottom electrode and a top electrode. The phase change is from a crystalline state to an amorphous state (or vise versa), and the phase change occurs when a current is caused to flow between the bottom electrode and the top electrode. The information stored in a cell is recognized using the difference in the level of resistance between the crystalline state and the amorphous state of the phase change material.
Furthermore, one of the most important factors when developing highly integrated phase change memory devices is to secure programming current. One way of securing programming current is to adopt PN diodes as switching elements in the phase change memory device. A phase change memory device having adopted the PN diodes provides advantages including improved current flow when compared to a CMOS (complementary metal-oxide semiconductor) transistor. With the improved current flow, it is possible to secure programming current, and additionally the size of cells can be decreased in comparison to a DRAM or a flash memory device.
In a typical phase change memory device, top electrode contacts are formed on the top electrodes to connect the top electrodes to bit lines. The top electrode contacts are formed simultaneously with the bit lines and have a thickness of approximately 5,000 Å.
This thickness (approximately 5,000 Å) is substantial, and thus etch loss is likely to occur in the top electrodes. If the overlap between the top electrodes and the top electrode contacts deviates even slightly from a preset range, the sidewalls of a phase change layer can be etched.
As a result, the material for top electrode contacts may not be appropriately deposited, leading to an open circuit between the bit lines and the top electrodes.